1. Field of the Invention
The present invention relates to an apparatus and a method of testing a semiconductor device. More particularly, the present invention relates to a probe pad for electrically testing a semiconductor device, a substrate on which a semiconductor device is formed, a method of testing a semiconductor device, and a tester for testing a semiconductor device.
2. Description of the Related Art
Generally, a semiconductor device may be manufactured by a deposition process, a photolithography process, an etching process, an ion implantation process, a metal wiring process, etc. The above processes may be repeatedly carried out to form a plurality of semiconductor devices (hereinafter, referred to as chips) on a substrate.
After the chips are formed on the substrate, an electric die sorting (EDS) process for electrically testing the chips is performed on the substrate. According to the EDS process, a pre-laser test for determining whether the chips are normal or abnormal is performed. A laser repair process for repairing repairable chips among the abnormal chips is executed. A post-laser test for determining whether the repaired chips are normal or abnormal is carried out. A final test is then performed for determining whether the chips are normal or abnormal under conditions that are different from those in the pre-laser test and the post-laser test.
In the EDS process, after electrical signals are applied to pads on each of the chips, outputted data is determined to be normal or abnormal. To input/output the electrical signals into/from the pads, probe needles for transmitting the electrical signals make contact with the pads, respectively.
However, when the number of semiconductor devices having high capacity increase, number of pads for inputting/outputting the electrical signals also increase. Also, to reduce time for testing the chips on the substrate, the chips are wholly tested through one EDS process by simultaneously contacting the probe needles with the pads.
Since the numbers of the pads are increased, the probe needles may not accurately make contact with the pads, respectively. Further, as described above, since several EDS processes are executed on one chip and the probe needles make contact with the pads in the respective EDS processes, the probe needles make contact with the pads several times. Therefore, it is quite important that the probe needles accurately make contact with the pads.
When the probe needle makes contact with an edge of the pad, the pad may be greatly damaged by the probe needle. Further, the contact between the probe needle and the edge of the pad may not be detected by an electrical open/short test so that a probe failure may be generated, thereby determining a corresponding chip to be abnormal. As a result, a normal chip is treated to be abnormal so that yield of manufacturing a semiconductor device may be greatly reduced.
A method for preventing damage of a semiconductor device due to a probe needle is disclosed in Japanese Patent Laid-Open Publication No. 1996-111431. According to the method, a probe pad is divided into an inclined probe region and a bonding region.
However, the probe pad may have an increased area due to the division of the probe pad. Also, when the probe needle makes contact with an edge of the probe pad, the above-mentioned probe failure may be generated. Further, the conventional method may not be employable in a wafer level package that is currently sold.